1. Field of the Invention
The present invention relates to technique for writing the analog voltage to an electrically writable and erasable non-volatile memory, thereby having the analog voltage memorized therein, and more particularly, relates to an electrical circuit capable of making use of this technique for well correcting unevenness in the write characteristics between memory cells and the deterioration of the write characteristic due to the endurance failure, thereby reducing unevenness in the analog voltage written to memory cells due to unevenness in the write characteristics between cells and improving the endurance or the life time of the memory cell.
2. Description of the Related Art
So far, various proposals have been made with respect to a method for memorizing a certain amount of analog electric charges in the non-volatile memory and a circuit capable of performing the same. For instance, the U.S. Pat. No. 5,638,320 (granted on Jun. 10, 1997) is an example of those proposals. This patent discloses a method for memorizing a desired amount of analog electric charges in the non-volatile memory and a circuit capable of doing the same (see the description from 6th line of page 16 to 19th line of page 18 of the specification thereof referring to reference figures shown as FIG. 12a on Sheet No. 29/63 through FIG. 15h on Sheet No. 40/63). The method disclosed by this patent is summarized as follows.
The threshold voltage value of the non-volatile memory is decreased with the increase of the write period of time. The variation amount of the threshold voltage per unit time is decreased and gets in the saturated state, eventually. This saturated threshold voltage is in proportion to the control voltage at the time of the write operation. This control voltage in proportion to the analog voltage is repetitively written to the non-volatile memory cell at a predetermined short write period of time (write operation). The threshold voltage of the memory cell is read out during the write operation and is compared with the analog voltage to be written (verify operation). This write/verify operations are repeated and the write operation is terminated when the threshold voltage as read out has reached the analog voltage to be written.
Furthermore, the above patent also discloses a method capable of improving the accuracy of the written analog voltage and shortening the write period of time. According to this method, the control voltage to be written during the repetitive write/verify operation and the time interval of the write/verify operation are made no to keep constant but to be variable (refer to reference figures shown as FIG. 15a on Sheet No. 33/63 through FIG. 15h on Sheet 40/63).
However, the purpose of this method is to finish the write operation of the analog voltage to a target non-volatile memory within a predetermined period of time as well as to improve the accuracy of the written analog voltage, regardless of the initial write speed of the memory cell. In general, however, the memory includes memory cells having an initial write speed which is made slow from the first or made slow due to the endurance deterioration. The method is trying to overcome this by means of expediting the initial write speed, for instance by setting the initial write control voltage to be higher than the ordinarily adopted voltage in proportion to the analog voltage and/or setting the pulse width of the initial write pulses to be narrower, thereby enhancing the efficiency of the electric charge injection. According to this method, however, some memory cells having a fast initial write speed might reach a predetermined analog voltage soon while the others might not. As a result, the accuracy of the written analog voltage can not be fine but be rough.
Therefore, there is no way but lowering the initial write speed in order to prevent the memory cell having a fast initial write speed from reaching the analog voltage at the time of the initial write operation. Accordingly, this method can not provide any effective countermeasure as far as the memory cell having a fast initial write speed concerns, so that it would be hard to say that the method adequately responds to such a purpose as described above.
The present invention has been made in consideration of the problems involved in the conventional circuit writing an analog voltage to the non-volatile memory. The object of the present invention is to provide a novel and improved circuit writing an analog voltage to the non-volatile memory, which makes it possible to improve the accuracy of the write voltage and also to shorten the write time as well.
In order to solve the problems as described above, according to the invention, there is provided an analog voltage supply circuit for a non-volatile memory (electrically writable and erasable). This circuit (100) includes a write voltage generation circuit (110) which generates a write voltage (Vpp) applied to a control gate of a memory cell in said non-volatile memory during write operation, based on an input analog voltage; a verify voltage generation circuit (120) which generates a verify voltage (VVFY) applied to said control gate during verify operation, based on said input analog voltage; a source voltage generation circuit (135) which generates a source voltage (VSource) applied to a source of said memory cell during write operation, wherein said source voltage is changed by varying the gain of an inverting amplifier by inputting a control signal (S0xcx9cS4); a multi-level sense amplifier (140) which compares the current mirror ratio current of the memory cell drain current with a reference comparison current (Iref) during verify operation; a counter decoder circuit (150) which outputs a signal equivalent to a predetermined number of write pulses to said memory cell; a comparison circuit (160) which compares the output of said multi-level sense amplifier with that of said counter decoder; and an up-down shift register circuit (170) which shifts the level of said control signals based on a comparison result obtained by said comparison circuit.
Furthermore, according to the invention, there is provided an analog voltage supply circuit for a non-volatile memory (electrically writable and erasable). This circuit (200) includes Analog voltage supply circuit for a non-volatile memory comprising: a write voltage generation circuit (110) which generates a write voltage (Vpp) applied to a control gate of a memory cell in said non-volatile memory during write operation, based on an input analog voltage; a verify voltage generation circuit (120) which generates a verify voltage (VVFY) applied to said control gate during verify operation, based on said input analog voltage; a source voltage generation circuit (135) which generates a source voltage (VSource) applied to a source of said memory cell during write operation, wherein said source voltage is changed by varying the gain of an inverting amplifier by inputting a control signal (S0xcx9cS4); a multi-level sense amplifier (140) which compares the memory cell drain current with the current mirror ratio current of a reference comparison current (Iref) during verify operation; a counter decoder circuit (150) which outputs a signal equivalent to a predetermined number of write pulses to said memory cell; a comparison circuit (160) which compares the output of said multi-level sense amplifier with that of said counter decoder; and an up-down shift register circuit (170) which shifts the level of said control signals based on a comparison result obtained by said comparison circuit.
Still further, according to the invention, there is provided an analog voltage supply circuit for a non-volatile memory (electrically writable and erasable). This circuit (300) includes a write voltage generation circuit (210) which generates a write voltage (Vpp) applied to a control gate of a memory cell in said non-volatile memory during write operation, based on an input analog voltage, and which changes write voltage by increasing the voltage of the electrode of an electric charge distribution condenser (C1) connected with the negative terminal of a condenser ratio amplifier as well as the voltage of another electrode of the condenser (C1) not connected with the same in response to the input of the first control signals (S0xcx9cS4); a verify voltage generation circuit (120) which generates a verify voltage (VVFY) applied to said control gate during verify operation, based on said input analog voltage; a source voltage generation circuit (235) which generates a verify source voltage (VVFYSource) applied to a source of said memory cell during verify operation, wherein said verify source voltage is changed by varying the gain of an inverting amplifier by inputting the second control signals (SX0xcx9cSX4); a sense amplifier (240) which compares the memory cell drain current with the reference comparison current (Iref) during verify operation; a counter decoder circuit which outputs a signal equivalent to a predetermined number of write pulses to said memory cell; and an up-down shift register circuit (170) which shifts the level of said first control signals (S0xcx9cS4) based on the output (SAOUT0) of said sense amplifier.
Still further, according to the invention, there is provided an analog voltage supply circuit for a non-volatile memory (electrically writable and erasable). This circuit (400) includes a write voltage generation circuit (110) which generates a write voltage (Vpp) applied to a control gate of the memory cell in said non-volatile memory during write operation, based on an input analog voltage; a verify voltage generation circuit (120) which generates a verify voltage (VVFY) applied to said control gate during verify operation, based on said input analog voltage; a source voltage generation circuit (135) which generates a source voltage (VVFYSource) applied to a source of said memory cell during write operation, wherein said source voltage is changed by changing the gain of an inverting amplifier by inputting the first control signals (S0xcx9cS4); a source voltage generation circuit (235) which generates a verify source voltage applied to a source of said memory cell during verify operation, wherein said output verify source voltage is changed by changing the gain of the inverting amplifier by inputting the second control signals (SX0xcx9cSX4); a sense amplifier (240) which compares the memory cell drain current with the reference comparison current during verify operation; a counter decoder circuit (150) which outputs a signal equivalent to a predetermined number of write pulses to said memory cell; and an up-down shift register circuit (170) which shifts the level of said first control signals based on a sense amplifier output.
Still further, according to the invention, there is provided an analog voltage supply circuit for a non-volatile memory (electrically writable and erasable). This circuit (500) includes a write voltage generation circuit (210) which generates a write voltage (Vpp) applied to a control gate of a memory cell in said non-volatile memory during write operation, based on an input analog voltage, and which changes write voltage by increasing the voltage of the electrode of an electric charge distribution condenser (C1) connected with the negative terminal of a condenser ratio amplifier as well as the voltage of another electrode of the condenser (C1) not connected with the same in response to the input of the first control signals (S0xcx9cS4); a verify voltage generation circuit (120) which generates a verify voltage (VVFY) applied to said control gate during verify operation, based on said input analog voltage; a write memory cell drain voltage generation circuit (VW voltage generation circuit 125) which generates a write memory cell drain voltage (VW voltage) during write operation, said write memory cell drain voltage is changed by varying the gain of a non-inverting amplifier; a multi-level sense (140) amplifier which compares the current mirror ratio current of the memory cell drain current with a reference comparison current (Iref) during verify operation; a counter decoder circuit (150) which outputs a signal equivalent to a predetermined number of write pulses to said memory cell; a comparison circuit (160) which compares the output of said multi-level sense amplifier with the output of said counter decoder; and an up-down shift register circuit (170) which shifts the level of said first control signals based on a comparison result of said comparison circuit.
Still further, according to the invention, there is provided an analog voltage supply circuit for a non-volatile memory (electrically writable and erasable). This circuit (600) includes a write voltage generation circuit (310) which generates a write voltage (Vpp) applied to a control gate of a memory cell in said non-volatile memory during write operation, based on an input analog voltage, and which changes the write voltage by increasing the voltage of the positive terminal of a condenser ratio amplifier of an electric charge distribution condenser (C1) in response to the input of the control signals (S0xcx9cS4); a verify voltage generation circuit (120) which generates a verify voltage (VVFY) applied to said control gate during verify operation, based on said input analog voltage; a write memory cell drain voltage generation circuit (VW voltage generation circuit 125) which generates a write memory cell drain voltage (VW voltage) during write operation, said write memory cell drain voltage is changed by varying the gain of a non-inverting amplifier; a multi-level sense amplifier (140) which compares the current mirror ratio current of the memory cell drain current with a reference comparison current during verify operation; a counter decoder circuit (150) which outputs a signal equivalent to a predetermined number of write pulses to said memory cell; a comparison circuit (160) which compares the output of said multi-level sense amplifier with the output of said counter decoder; and an up-down shift register circuit (170) which shifts the level of said control signals based on a comparison result of said comparison circuit.
Still further, according to the invention, there is provided an analog voltage supply circuit for a non-volatile memory (electrically writable and erasable). This circuit (700) includes a write voltage generation circuit (210) which generates a write voltage (Vpp) applied to a control gate of a memory cell in said non-volatile memory during write operation, based on an input analog voltage, and which changes the write voltage by increasing the voltage of the electrode of an electric charge distribution condenser (C1) connected with the negative terminal of a condenser ratio amplifier as well as the voltage of another electrode of the condenser (C1) not connected with the same in response to the input of the control signals; a verify voltage generation circuit (120) which generates a verify voltage (VVFY) applied to said control gate during verify operation, based on said input analog voltage; a write memory cell drain voltage generation circuit (VW voltage generation circuit 125) which generates a write memory cell drain voltage (VW voltage) during write operation, said write memory cell drain voltage is changed by varying the gain of a non-inverting amplifier; a multi-level sense amplifier (240) which compares the memory cell drain current with the current mirror ratio current of the reference comparison current (Iref) during verify operation; a counter decoder circuit (150) which outputs a signal equivalent to a predetermined number of write pulses to said memory cell; a comparison circuit (160) which compares the output of said multi-level sense amplifier with the output of said counter decoder; and an up-down shift register circuit (170) which shifts the level of said control signals based on a comparison result of said comparison circuit.
Still further, according to the invention, there is provided an analog voltage supply circuit for a non-volatile memory (electrically writable and erasable). This circuit (800) includes a write voltage generation circuit (310) which generates a write voltage (Vpp) applied to a control gate of a memory cell in said non-volatile memory during write operation, based on an input analog voltage, and which changes the write voltage by increasing the voltage of the positive terminal of a condenser ratio amplifier of an electric charge distribution condenser by inputting the control signals (S0xcx9cS4); a verify voltage generation circuit (120) which generates a verify voltage (VVFY) applied to said control gate during verify operation, based on said input analog voltage; a write memory cell drain voltage generation circuit (VW voltage generation circuit 125) which generates a write memory cell drain voltage (VW voltage) during write operation, said write memory cell drain voltage is changed by varying the gain of a non-inverting amplifier; a multi-level sense amplifier (240) which compares the memory cell drain current with the specific current mirror current of the reference comparison current during verify operation; a counter decoder circuit (150) which outputs a signal equivalent to a predetermined number of write pulses to said memory cell; a comparison circuit (160) which compares the output of said multi-level sense amplifier with the output of said counter decoder; and an up-down shift register circuit (170) which shifts the level of said control signals based on a comparison result of said comparison circuit.